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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P316B
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75P316B is a product of the PD75316B with its built-in ROM having been replaced with the onetime PROM. It is most suitable for test production during system development and for production in small amounts since it can operate under the same supply voltage as mask products. The one-time PROM product is capable of writing only once and is effective for production of many kinds of sets in small quantities and early startup. The EPROM product allows programs to be written and rewritten, making it ideal for system evaluation. Functions are described in detail in the following User'S Manual, which should be read when carrying out design work. PD75308 User's Manual: IEM-5016
FEATURES
* Compatible (excluding mask option) with the PD75312B/75316B (mask products) * Memory capacity * Program memory (PROM) : 16256 x 8 bits * Data memory (RAM) : 1024 x 4 bits * Ideal for small set as camera, etc.
ORDERING INFORMATION
Ordering Code PD75P316BGC-3B9 Package 80-pin plastic QFP (s 14 mm) s 80-pin plastic QFP (fine pitch) (s 12 mm) s 80-pin ceramic WQNF (LCC with window) Internal ROM One-time PROM Quality Grade Standard
PD75P316BGK-BE9 PD75P316BKK-T*
* Under Development
One-time PROM Standard EPROM Not applicable (for function evaluation)
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The PD75P316B EPROM product does not provide a level of reliability suitable for use as a volume production product for customers' devices. The EPROM product should be used solely for function evaluation in experiments or preproduction. In descriptions common to one-time PROM products and EPROM products in this document, the term "PROM" is used.
The information in this document is subject to change without notice.
Document No. IC-3189 (O.D. No. IC-8696) Date Published January 1994P Printed in Japan
The mark 5 shows the major revised points.
(c) NEC Corporation 1994
PD75P316B
PIN CONFIGURATION (Top View) * 80-pin plastic QFP (s 14 mm) s
P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7
1 2 3 4 5 6 7 8 9
8079787776 757473 7271 70696867666564636261
S1 S0 RESET
* 80-pin plastic TQFP (fine pitch)(s 12 mm) s * 80-pin ceramic WQFN (LCC with window)
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P60/KR0 X2 X1 VPP* XT2 XT1 VDD P33/MD3 P32/MD2 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1
PD75P316BGC-3B9 PD75P316BGK-BE9 PD75P316BKK-T
10 11 12 13 14 15 16 17 18
19 20 2122232425 262728 2930 31323334353637383940
P53 P00/INT4
*
In normal operation, VPP input should be the VDD level. P00-03 P10-13 P20-23 P30-33 P40-43 P50-53 P60-63 P70-73 BP0-7 KR0-7 SCK SI SO SB0, 1 RESET S0-31 COM0-3 : Port 0 : : : : : : : : : : : : : : : : Port Port Port Port 1 2 3 4 VLC0-2 BIAS LCDCL SYNC TI0 PTO0 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 MD0-3 VDD VSS VPP
: LCD Power Supply 0-2 : : : : : : : : : : : : LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 Programmable Timer Output 0 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Mode Selection
Port 5 Port 6 Port 7 Bit Port Key Return Serial Clock Serial Input Serial Output Serial Bus 0, 1 Reset Input Segment Output 0-31 Common Output 0-3
: Positive Power Supply : Ground : Programing/Verifying Power
2
P01/SCK P02/SO/SB0
COM3 BIAS VLC0 VLC1 VLC2
COM0
COM1 COM2
P41 P42 P43 VSS
P40
P50
P51 P52
BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT PROGRAM COUNTER (14) ALU SP(8) CY
PORT0
4
P00-P03
PORT1
4
P10-P13
TI0/P13 PTO0/P20
TIMER/EVENT COUNTER #0 INTT0
PORT2
4
P20-P23 P30-P33 /MD0-MD3 P40-P43
BANK
PORT3
4
PORT4 BUZ/P23 WATCH TIMER PROGRAM MEMORY (PROM) SI/SB1/P03 SO/SB0/P02 SCK/P01 SERIAL BUS INTERFACE INTCSI 16256 x 8 BITS DECODE AND CONTROL GENERAL REG. PORT5
4
4
P50-P53
INTW
fLCD
m
INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR7/P73
8
PORT6 DATA MEMORY (RAM) 1024 x 4 BITS
4
P60-P63
PORT7
4
P70-P73
24 8
INTERRUPT CONTROL LCD CONTROLLER /DRIVER CPU CLOCK fLCD
S0-S23 S24/BP0 -S31/BP7 COM0-COM3 VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31
4 3
BIT SEQ. BUFFER (16)
fX / 2 SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER SUB MAIN CONTROL CONTROL PCL/P22 XT1 XT2 X1 X2
N
PD75P316B
VPP VDD VSS RESET
3
PD75P316B
CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................... 5
1.1 1.2 1.3 PORT PINS ........................................................................................................................................................... 5 OTHER PINS ......................................................................................................................................................... 7 PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9
2. 3. 4.
DIFFERENCES BETWEEN PRODUCTS IN SERIES ................................................................................ 11 DATA MEMORY (RAM) ............................................................................................................................ 12 PROGRAM MEMORY WRITE AND VERIFY ............................................................................................ 14
4.1 4.2 4.3 4.4 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 14 PROGRAM MEMORY WRITING PROCEDURE ............................................................................................... 15 PROGRAM MEMORY READING PROCEDURE ............................................................................................... 16 ERASURE PROCEDURE(PD75P316BKK-T-ONLY) ........................................................................................ 17
5. 6. 7.
ELECTRICAL SPECIFICATIONS ............................................................................................................... 18 PACKAGE INFORMATION ....................................................................................................................... 39 RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 42
APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 43 APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 44
4
PD75P316B
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Pin Name P00 P01 P02 P03 P10 P11 Input P12 P13 P20 P21 Input/output P22 P23 P30 *2 P31 *2 Input/output P32 *2 P33 *2 MD2 MD3 N-ch open-drain 4-bit input/output port (PORT 4). Data input/output pins for program memory (PROM) write/verify (low-order 4 bits). PCL BUZ LCDCL SYNC MD0 MD1 Programmable 4-bit input/output port (PORT3) Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. x INT2 TI0 PTO0 -- 4-bit input/output port (PORT2) Internal pull-up resistor specification by software is possible as a 4-bit unit. x Input/Output Input Input/output Input/output Input/output Dual-Function Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 With noise elimination circuit 4-bit input port (PORT1) Internal pull-up resistor specification by software is possible as a 4-bit unit. x 4-bit input port (PORT0) Internal pull-up resistor specification by software is possible for P01 to P03 as a 3-bit unit. x Function 8-bit I/O Afer Reset I/O Circuit Type*1 B F -A Input F -B M-C
Input
B -C
Input
E-B
Input
E-B
P40 to P43*2
Input/output
--
High impedance
M-A
P50 to P53 *2
Input/output
--
N-ch open-drain 4-bit input/output port (PORT 5) Data input/output pins for program memory (PROM) write/verify (high-order 4 bits).
High impedance
M-A
P60 P61 P62 P63 P70 P71 P72 P73 Input/output Input/output
KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 4-bit input/output port (PORT7). Internal pull-up resistor specification by software is possible as a 4-bit unit. Programmable 4-bit input/output port (PORT6). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit.
Input
F -A
Input
F -A
* 1. 2.
: Indicates a Schmitt-triggered input. Direct LED drive capability.
5
PD75P316B
1.1
PORT PINS (2/2)
Pin Name BP0 BP1
Input/Output
DualFunction Pin S24 S25
Function
8-bit I/O
After Reset
I/O Circuit TYPE
Output BP2 S26 S27 S28 S29 Output BP6 BP7 S30 S31 1-bit output port (BIT PORT) Dual-function as segment output pins. x
5
BP3 BP4 BP5
*
G-C
* For BP0 to BP7, VLC1 is selected as the input source. The output level depends on BP0 to BP7 and the VLC1 external circuit, however.
6
PD75P316B
1.2
OTHER PINS
Pin Name TI0 PTO0 PCL BUZ SCK SO/SB0 Input/Output Input output Input/output Input/output Input/output Input/output DualFunction Pin P13 P20 P22 P23 P01 P02 Function External event pulse input pin for timer/event counter. Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or system clock trimming) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data input pin Serial bus input/output pin Edge-detected vectored interrupt input pin (rising or falling edge detection). Edge-detected vectored interrupt input pin (detection edge selectable) Edge-detected testable input pin (rising edge detection) Testable Input/output pins (parallel falling edge detection) Testable Input/output pins (parallel falling edge detection) Segment signal output pins Segment signal output pins Common signal output pins LCD drive power supply pins External split cutting output pin External extension driver drive clock output pin External extension driver synchronization clock output pin Main system clock oscillation crystal/ceramic connection pins. When an external clock is used, the clock is input to X1 and the inverted clock to X2. Subsystem clock oscillation crystal connection pins When an external clock is used, the clock is input to XT1 and the inverted clock toXT2. XT1 can be used as a 1-bit input (test) pin. System reset input pin (low-level active). Mode selection pin for program memory (PROM) write/ verify. Program voltage application pin for program memory (PROM) write/verify . Connected to VDD in normal operation. Applies +12.5 V in program memory write/ verify. Positive power supply pin GND potential pin After Reset -- Input Input Input Input Input I/O Circuit Type *1 B -C E-B E-B E-B F -A F -B M-C
SI/SB1
Input/output
P03
Input
INT4 INT0
Input
P00 P10 P11
--
B
Input INT1 INT2 KR0 to KR3 KR4 to KR7 S0 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL*2 SYNC*2 Input Input/output Input/output Output Output Output -- -- Input/output Input/output
-- -- Input Input *3 *3 *3 -- High impedance Input Input
B -C
P12 P60 to P63 P70 to P73 -- BP0 to 7 -- -- -- P30 P31
B -C F -A F -A G-A G-A G-B -- -- E-B E-B
X1, X2
Input
--
--
--
XT1, XT2
Input
--
--
--
RESET MD0 to MD3
Input
-- P30 to P33
-- Input
B E-B
Input/output
VPP
--
--
--
--
VDD VSS
-- --
-- --
-- --
-- --
7
PD75P316B
*
1. : Indicates a Schmitt-triggered input. 2. Pins provided for future system expansion. Currently used only as pins 30 and 31. 3. VLCX shown below can be selected for display outputs. S0 to S31: VLC1, COM0 to COM2: VLC2 , COM3: VLC0 However, display output levels depend on the display output and VLCX external circuit.
8
PD75P316B
1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits for each of the pin PD75P316B are shown below in partially simplified form.
TYPE A (For TYPE E-B) TYPE D (For TYPE E-B, F-A) VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT
Push-pull output that can be made high-impedance output CMOS Standard Input Buffer TYPE B (P-ch and N-ch OFF) TYPE E-B
VDD P.U.R. P.U.R. enable data Type D output disable P-ch
IN
IN/OUT
Type A
P.U.R.:Pull-Up Resistor
Schmitt-Trigger Input with Hysteresis Characteristic
TYPE B-C
TYPE F-A
VDD
VDD P.U.R. P.U.R. enable
P.U.R. enable data Type D output disable
P.U.R. P-ch
P-ch
IN/OUT
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R.:Pull-Up Resistor
9
PD75P316B
TYPE F-B
VDD P.U.R. P.U.R. enable P-ch VDD P-ch
TYPE G-O 5
VDD P-ch VLC0
output disable (P) data output disable output disable (N)
IN/OUT
VLC1 P-ch SEG data/ Bit Port data N-ch VLC2 N-ch
N-ch
OUT
P.U.R.:Pull-Up Resistor
TYPE G-A
TYPE M-A
IN/OUT
VLC0 P-ch VLC1 P-ch SEG data N-ch VLC2 N-ch
Middle-High Voltage Input Buffer (+10 V Withstand Voltage) output disable data N-ch (+10 V Withstand Voltage)
OUT
TYPE G-B
TYPE M-C
VDD
VLC0 VLC1 P-ch N-ch P-ch
P.U.R. P.U.R. enable P-ch IN/OUT
OUT COM data N-ch VLC2 N-ch P-ch
data output disable
N-ch
P.U.R.:Pull-Up Resistor
10
PD75P316B
2. DIFFERENCES BETWEEN PRODUCTS IN SERIES
The PD75P316B is a version of the PD75316B with its built-in mask ROM replaced with the one-time PROM or EPROM. When performing debugging or preproduction of an application system using PROM and then volume production using a mask ROM product, etc., these differences should be taken into account in the transition. Table 2-1 shows the differences from the other products in series. For the details of the CPU functions and the built-in hardware, please refer to the PD75308 User's Manual (IEM-5016). Table 2-1 Differences between Products in Series
Product Name Comparison Item Program memory (bytes)
PD75P316A
* EPROM/one-time PROM * 16256
PD75P316B
* One-time PROM * EPROM * 16256 1024 None None
PD75312B/75316B
* Mask ROM * 12160/16256
Data memory (x 4 bits) Pull-up resistors of ports 4 and 5 LCD driving power supplying split resistor No.50 to 55 Pin connection No.57
Incorporation specifiable by mask option Incorporation specifiable by mask option P30 to P33 IC
P30/MD0 to P33/MD3 VPP
5
Electrical specifications Power supply voltage range
The mask ROM products and PROM products have different consumption currents, etc. See the Electrical Specifications section in the relevant Data Sheets for details. 2.7 to 6.0 V * 80-pin plastic QFP (14 x 20 mm) * 80-pin ceramic WQNF (LCC with window) 2.0 to 5.5 V * 80-pin plastic QFP (s 14 mm) s * 80-pin plastic TQFP (fine pitch)(s 12 mm) s * 80-pin ceramic QWFN (LCC with window) * 80-pin plastic QFP (s 14 mm) s * 80-pin plastic TQFP (fine pitch)(s 12 mm) s
5
Package
Other
The mask ROM products and PROM products have different circuit scales and mask layouts, and therefore differ in terms of noise resistance and noise radiation.
5 5
*
Noise resistance and noise radiation differs between the PROM products and mask ROM products. When investigating a switch from PROM product to mask PROM product in the transition from preproduction to volume production, thorough evaluation should be carried out with the mask ROM CS product (not the ES product).
11
PD75P316B
3. DATA MEMORY (RAM)
Fig. 3-1 shows the data memory configuration. It consists of a data area and a peripheral hardware area. The data area consists of memory banks 0 to 3 with each bank consisting of 256 words x 4 bits. Peripheral hardware has been assigned to the area of memory bank 15. (1) Data area The data area comprises a static RAM. It is used to store program data and as a subroutine, interrupt execution stack memory. Even if the CPU operation is stopped in the standby mode, it is possible to hold the memory content for a long time by battery backup, etc. The data area is operated by memory manipulation instructions. The static RAM has been mapped to memory banks 0, 1, 2 and 3 by 256 x 4 bits each. Bank 0 has been mapped as a data area but is also available as a general register area (000H to 007H) and a stack area (000H to 0FFH) (banks 1, 2 and 3 are available only as a data area). In the static RAM, 1 address consists of 4 bits. It can be operated in units of 8 bits by 8-bit memory manipulation instructions or in bits by bit manipulation instructions, however. In an 8-bit manipulation instruction, an even address should be specified. (a) General register area The general register area can be operated either by general register operation instructions or by memory manipulation instructions. Up to eight 4-bit registers are available. That part of the 8 general registers which is not used in the program is available as a data area or a stack area. (b) Stack area The stack area is set by an instruction. It is available as a subroutine execution or interrupt service execution save area. (2) Peripheral hardware area The peripheral hardware area has been mapped to F80H to FFFH of memory bank 15. It is operated by memory manipulation instructions just as the static RAM. In the peripheral hardware, however, the operable bit unit differs from one address to another. An address to which peripheral hardware has not been assigned is inaccessible since no data memory is built in.
12
PD75P316B
Fig. 3-1 Data Memory Map
Data Memory General Register Area Stack Area 000H (8 x 4) 007H 008H 256 x 4 0FFH 100H Data Area Static RAM (1024 x 4) 256 x 4 1FFH 200H 256 x 4 2FFH 300H 256 x 4 3FFH Not On-Chip
Memory Bank
0
1
2
3
F80H Peripheral Hardware Area FFFH 128 x 4 15
13
PD75P316B
4. PROGRAM MEMORY WRITE AND VERIFY
The ROM built into the PD75P316B is a 16256 x 8-bit electrically writable one-time PROM. The table below shows the pins used to program this PROM. There is no address input; instead, a method to update the address by the clock input via the X1 pin is adopted.
Pin Name VPP
Function Voltage applecation pin for program memory write/verify (normally VDD potential). Address update clock inputs for program memory write/ verify. Inverse of X1 pin signal is input to X2 pin. Operating mode selection pin for program memory write/ verify.
X1, X2
MD0 to MD3
P40 to P43 (low-order 4 bits) 8-bit data input/output pins for progrm memory write/ P50 to P53 (high-order 4 bits) verify. VDD Supply voltage application pin. Applies 2.0 to 5.5 V in normal operation, and 6 V for program memory write/verify.
4.1
PROGRAM MEMORY WRITE/VERIFY OPERATING MODES
The PD75P316B assumes the program memory write/verify mode when +6 V and +12.5 V are applied respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin setting in this mode. All the remaining pins are at the VSS potential by the pull-down resistor.
Operating Mode Setting Operating Mode VPP VDD MD0 H L +12.5 V +6 V L H X: L or H L X H H H H Verify mode Program inhibit mode MD1 L H MD2 H H MD3 L H Program memory address zero-clear Write mode
14
PD75P316B
4.2 PROGRAM MEMORY WRITING PROCEDURE The program memory writing procedure is shown below. High-speed write is possible. (1) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level. (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) Supply 5 V to the VDD and VPP pins. 10 s wait. The program memory address 0 clear mode. Supply 6 V and 12.5 V respectively to VDD and VPP. The program inhibit mode. Write data in the 1-ms write mode. The program inhibit mode. The verify mode. If written, proceed to (10); if not written, repeat (7) to (9). (Number of times written in (7) to (9): X) x 1-ms additional write. The program inhibit mode. Update (+1) the program memory address by inputting 4 pulses to the X1 pin. Repeat (7) to (12) up to the last address.
(14) The program memory address 0 clear mode. (15) Change the VDD and VPP pins voltage to 5 V. (16) Power off. The diagram below shows the procedure of the above (2) to (12).
Repeated X Times
Write
Verify
Additional Write
Address Increment
VPP VPP VDD VDD + 1 VDD VDD
X1
P40-P43 P50-P53
Data Input
Data Output
Data Input
MD0 (P30)
MD1 (P31)
MD2 (P32)
MD3 (P33)
15
PD75P316B
4.3 PROGRAM MEMORY READING PROCEDURE The PD75P316B can read the content of the program memory in the following procedure. It reads in the verify mode. (1) (2) (3) (4) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level. Supply 5 V to the VDD and VPP pins. 10 s wait. The program memory address 0 clear mode.
(5) Supply 6 V and 12.5 V respectively to VDD and VPP. (6) The program inhibit mode. (7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) (9) (10) (11) The program inhibit mode. The program memory address 0 clear mode. Change the VDD and VPP pins voltage to 5 V. Power off. The diagram below shows the procedure of the above (2) to (9).
VPP VPP VDD
VDD + 1 VDD VDD
X1
P40-P43 P50-P53
Data Output
Data Output
MD0 (P30)
MD1 (P31)
"L"
MD2 (P32)
MD3 (P33)
16
PD75P316B
4.4 ERASURE PROCEDURE (PD75P316BKK-T ONLY) The data programmed in the PD75P316B can be erased by exposure to ultraviolet radiation through the window in the top of the package. Erasure is possible using ultraviolet light with a wavelength of approximately 250 nm. The exposure required for complete erasure is 15 W.s/cm2 (UV intensity x erasure time). Erasure takes aproximately 15 to 20 minutes using a commercially available UV lamp (254 nm wavelength, 12 mW/cm2 intensity). Note 1. Program contents may also be erased by extended exposure to direct sunlight or fluorescent light. The contents should therefore be protected by masking the window in the top of the package with light-shielding film. The light-shielding film provided with NEC's UV EPROM products should be used. Erasure should normally be carried out at a distance of 2.5 cm or less from the UV lamp. The erasure time may be increased due to deterioration of the UV lamp or dirt on the package window.
2. Remarks
17
PD75P316B
5. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER Supply voltage Input voltage Output voltage Output current high SYMBOL VDD VI1 VI2 VO Except ports 4 & 5 Ports 4 & 5 TEST CONDITIONS RATING -0.3 to + 7.0 -0.3 to VDD + 0.3 -0.3 to + 11 -0.3 to VDD + 0.3 1 pin All pins 1 pin Peak value R.m.s. value Output current low -15 -30 30 15 100 60 100 60 -40 to + 85 -65 to + 150 UNIT V V V V mA mA mA mA mA mA mA mA C C
IOH
IOH*
Total for ports 0, 2, 3, 5
Peak value R.m.s. value
Total for ports 4, 6, 7 Operating temperature Storage temperature Topt Tstg
Peak value R.m.s. value
*
The r.m.s. value should be calculated as follows [R.m.s. value] = [Peak value] x Duty
Note
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance I/O capacitance SYMBOL CIN COUT CIO f=1 MHz Unmeasured pins returned to 0 V. TEST CONDITIONS MIN. TYP. MAX. 15 15 15 UNIT pF pF pF
18
PD75B316B
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.0 to 6.0 V)
RESONATOR RECOMENDED CONSTANT
X1 X2
PARAMETER Oscillation frequency (fXX)*1
TEST CONDITIONS
MIN. TYP. MAX. UNIT
1.0
5.0*3
MHz
Ceramic resonator*3
C1
C2
Oscillation stabilization time*2 Oscillation frequency (fXX)*1
After VDD has reached MIN. of oscillation voltage range.
4
ms
VDD X1 X2
1.0 VDD=4.5 to 6.0 V
4.19
5.0*3 10 30
MHz ms ms
Crystal*3
C1 VDD
C2
Oscillation stabilization time*2 X1 input frequency
X1
X2
External clock
PD74HCU04
(fX)*1 X1 input high-/low-level width (tXH, tXL)
1.0
5.0*3
MHz
100
500
ns
*
1. The oscillation frequency and X1 input frequency are only indications of the oscillator characteristics. See the AC characteristics for instruction execution times. 2. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range, or the STOP mode is released. 3. When the oscillation frequency is 4.19 MHz < fXX <= 5.0MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle will be less than 0.95 us, and the MIN. value of 0.95 us in the specification will not be achieved.
Note
When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VDD. Do not connect to a ground pattern carrying a high current. * A signal should not be taken from the oscillator.
19
PD75P316B
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.0 to 6.0 V)
RESONATOR RECOMENDED CONSTANT
XT1 XT2 R C1 C2
PARAMETER Oscillation frequency (fXT) Oscillation stabilization time* XT1 input frequency
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
32
32.768
35
kHz
Crystal resonator
VDD=4.5 to 6.0 V
1.0
2 10
s s
VDD
XT1
XT2 Open
External clock
(fXT) XT1 input high-/lowlevel width (tXTH, tXTL)
32
100
kHz
5
15
s
*
This is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range.
Note
When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VDD. Do not connect to a ground pattern carrying a high current. * A signal should not be taken from the oscillator. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used.
20
PD75B316B
(1) VDD=2.7 to 6.0 V
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL VIH1 Input voltage high VIH2 VIH3 VIH4 VIL1 Input voltage low VIL2 VIL3 Ports 2 and 3 Ports 0, 1, 6, 7 and RESET Ports 4 and 5 X1, X2, XT1 Ports 2, 3, 4, 5 Ports 0, 1, 6, 7 and RESET X1, X2, XT1 VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A VDD = 4.5 to 6.0 V IOH = -100 A IOH = -30 A Ports 3, 4, 5 VDD = 4.5 to 6.0 V IOL = 15 mA Ports 0, 2, 3, 4, 5, 6, 7 VOL1 Output voltage low SB0, 1 VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A Open-drain pull-up resistor 1 k VDD = 4.5 to 6.0 V IOL = 100 A IOL = 50 A Other than below VIN = VDD ILIH2 ILIH3 Input leakage current low ILIL1 VIN = 0 V ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 10 V VOUT = 0 V X1, X2, XT1 Other than below Ports 4 and 5 -20 3 20 -3 VIN = 10 V X1, X2, XT1 Ports 4 and 5 Other than below 20 20 -3 TEST CONDITIONS MIN. 0.7 VDD 0.8 VDD 0.7 VDD VDD -0.5 0 0 0 VDD -1.0 VDD -0.5 VDD -2.0 VDD -1.0 TYP. MAX. VDD VDD 10 VDD 0.3 VDD 0.2 VDD 0.4 UNIT V V V V V V V V V V V
VOH1 Output voltage high VOH2
Ports 0, 2, 3, 6, 7, and BIAS
BP0 to BP7 (with 2 IOH outputs)
0.7
2.0
V
0.4 0.5 0.2 VDD 1.0 1.0 3
V V V V V
VOL2
BP0 to BP7 (with 2 IOL outputs)
IL1H1 Input leakage current high
A A A A A A A A
Output leakage current high Output leakage current low
21
PD75P316B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER Internal pull-up resistor LCD drive voltage LCD output voltage deviation*1 (common) LCD output voltage deviation (segment) SYMBOL TEST CONDITIONS Ports 0, 1, 2, 3, 6, 7 (Except P00) VIN = 0 V VDD = 5.0 V 10% VDD = 3.0 V 10% MIN. 15 30 2.0 IO = 5 A TYP. 40 MAX. 80 200 VDD 0.2 UNIT k k V
RL
VLCD
VODC
VODS
IO = 1 A
VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.7 V VLCD VDD
0
V
0
0.2 4.0 0.5 1 300 30 7 1 0.5 12 1.5 3 900 90 21 25 15 5
V
VDD = 5 V 10%*4 IDDI 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF IDD2 VDD = 3 V 10%*5 HALT mode VDD = 5 V 10% VDD = 3 V 10%
mA mA mA
A A A A A A
Supply current*2
IDD3 IDD4 32 kHz*6 crystal oscillation
VDD = 3 V 10% HALT mode VDD = 3 V 10%
VDD = 5 V 10% IDD5 XT1 = 0 V STOP mode VDD = 3 V 10%
Ta = 25 C
0.5
* 1. The voltage deviation is the difference between the output voltage and the ideal value of the common output (VLCDn; n = 0, 1, 2). 2. Excluding the current flowing in the internal pull-up resistor. 3. 4. 5. 6. Including the case where the subsystem clock is oscillated. When the processor clock control register (PCC) is set to 0011 for operation in high-speed mode. When PCC is set to 0000 for operation in low-speed mode. When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and the device is operated on the subsystem clock.
22
PD75B316B
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER CPU clock cycle time*1 (minimum instruction execution time = 1 machine cycle) TI0 input frequency SYMBOL TEST CONDITIONS Operating on main system clock Operating on subsystem clock VDD = 4.5 to 6.0 V fTI 0 tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 1.8 INT0 tINTH, tINTL INT1, 2, 4 KR0 to KR7 RESET low-level width tRSL *2 10 10 10 275 kHz VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 122 TYP. MAX. 64 64 125 1 UNIT
s s s
MHz
tCY
TI0 input high-/lowlevel width
s s s s s s
Interrupt input high-/low-level width
* 1. The CPU clock () cycle time (minimum instruction execution time) is determined by the oscillation frequency of the connected resonator, the system clock control register (SCC), and the processor control register (PCC). The graph on the right shows the characteristic of the cycle time tCY against the supply current VDD in the case of main system clock operation. 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
tCY vs VDD (Operating on Main System Clock)
70 64 30 6 5 4
Guaranteed Operation Range
Cycle Time tCY [s]
3
2
1
0.5 0 1 2 3 4 5 6
Supply Voltage VDD [V]
23
PD75P316B
SERIAL TRANSFER OPERATIONS 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 3800 SCK high-/low-level width SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL1 tKH1 VDD = 4.5 to 6.0 V tKCY1/2-50 tKCY1/2-150 150 ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns
tSIK1
tKSI1 * tKSO1 RL = 1 k, CL = 100 pF VDD = 4.5 to 6.0 V
400 250 1000
ns ns ns
2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 SCK high-/low-level width SI setup time (to SCK) SI hold time (from SCK ) SO output delay time from SCK tKL2 tKH2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK2
tKSI2 * tKSO2 RL = 1 k, CL = 100 pF VDD = 4.5 to 6.0 V
400 300 1000
ns ns ns
*
RL and CL are the SO output line load resistance and load capacitance.
24
PD75B316B
SBI Mode (SCK ... Internal clock output (Master)): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY3 3800 SCK high-/low-level width SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tKL3 tKH3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 150 ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns
tSIK3
tKSI3 RL = 1 k, CL = 100 pF * VDD = 4.5 to 6.0 V
tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns ns
tKSO3
tKSB tSBK tSBL tSBH
SBI Mode (SCK ... External clock input (Slave)): (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY4 3200 SCK high-/low-level width SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tKL4 tKH4 VDD = 4.5 to 6.0 V 400 1600 tSIK4 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tKSI4 VDD = 4.5 to 6.0 V
tKCY4/2 0 0 300 1000
ns ns ns ns ns ns ns
tKSO4
RL = 1 k, CL = 100 pF
*
tKSB tSBK tSBL tSBH
tKCY4 tKCY4 tKCY4 tKCY4
*
RL and CL are the SB0, 1 output line load resistance and load capacitance.
25
PD75P316B
(2) VDD=2.7 to 6.0 V
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL VIH1 Input voltage high VIH2 VIH3 VIH4 VIL1 Input voltage low VIL2 VIL3 VOH1 Output voltage high VOH2 TEST CONDITIONS Ports 2 and 3 Ports 0, 1, 6, 7 and RESET Ports 4 and 5 X1, X2, XT1 Ports 2, 3, 4, 5 Ports 0, 1, 6, 7 and RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7 and BIAS BP0 to BP7 (with 2 IOH outputs) Ports 0, 2, 3, 4, 5 6, 7 VOL1 Output voltage low VOL2 ILIH1 Input leakage current high VIN = VDD ILIH2 ILIH3 Input leakage current low ILIL1 VIN = 0 V ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 10 V VOUT = 0 V Ports 0, 1, 2, 3, 6, 7 (Except P00) VIN = 0 V X1, X2, XT1 Other than below Ports 4 and 5 -20 3 20 -3 VIN = 10 V X1, X2, XT1 Ports 4 and 5 Other than below 20 20 -3 SB0, 1 BP0 to BP7 (with 2 IOL outputs) Open-drain, pull-up resistor 1 k IOL = 10 A Other than below 0.2 VDD V IOH = -100 A IOH = -10 A IOL = 400 A MIN. 0.8 VDD 0.8 VDD 0.8VDD VDD -0.3 0 0 0 VDD -0.5 TYP. MAX. VDD VDD 10 VDD 0.2 VDD 0.2 VDD 0.25 UNIT V V V V V V V V
VDD -0.4
V
0.5
V
0.4 3
V
A A A A A A A A
Output leakage current high Output leadage current low Internal pull-up resistor LCD drive voltage
RL
VDD = 2.5 V 10%
50
600
k
VLCD
2.0
VDD
V
26
PD75B316B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER LCD output voltage deviation *1 (common) LCD output voltage deviation (segment) SYMBOL IO = 5 A TEST CONDITIONS MIN. TYP. MAX. 0.2 UNIT
VODC
VODS
IO = 1 A
VLCDO = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.0 V VLCD VDD
0
V
0
0.2
V
VDD = 3 V 10%*4 IDDI 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF low-speed mode VDD = 2.5 V 10%*4 HALT mode VDD = 3 V 10% VDD = 2.5 V 10%
0.5 0.4 300 200 40 25 7 4 0.5
1.5 1.2 900 600 90 75 21 12 15 5 15 5
mA mA
A A A A A A A A A A
IDD2
VDD = 3 V 10% IDD3 Supply current*2 32 kHz*5 crystal oscillation IDD4 mode VDD = 2.5 V 10% HALT VDD = 3 V 10% VDD = 2.5 V 10%
VDD = 3 V 10% IDD5 XT1 = 0 V STOP mode VDD = 2.5 V 10% Ta = 25C
0.5 0.4
Ta = 25C
0.4
* 1. The voltage deviation is the difference between the output voltage and the ideal value of the common output (VLCDn; n = 0, 1, 2). 2. Excluding the current flowing in the internal pull-up resistor. 3. Including the case where the subsystem clock is oscillated. 4. When PCC is set to 0000 for operation in low-speed mode. 5. When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and the device is operated on the subsystem clock.
27
PD75P316B
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 2.7 to 6.0 V CPU clock cycle time (minimum instruction execution time = 1 machine cycle)*1 Operating on main system clock tCY VDD = 2.0 to 6.0 V Ta = -40 to + 60 C VDD = 2.2 to 6.0 V MIN. 3.8 5 3.4 TYP. MAX. 64 64 64 UNIT
s s s s
Operating on subsystem clock fTI tTIH, tTIL INT0
114
122
125
TI0 input frequency TI0 input high-/lowlevel width
0
275
kHz
1.8 *2 10 10 10
s s s s s
Interrupt input high-/low-level width
tINTH, tINTL
INT1, 2, 4 KR0 to KR7
RESET low-level width
tRSL
* 1. The CPU clock ( ) cycle time (minimum instruction execution time) is determined by the oscillation frequency of the connected resonator, the system clock control register (SCC), and the processor clock control register (PCC). The graph on the right shows the characteristic of the cycle time tCY against the supply current VDD in the case of main system clock operation. 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IMO).
Cycle Time tCY [s]
tCY vs VDD (Operating on Main System Clock)
70 64 30 6 5 4 3
Guaranteed Operation Range
2
1
0.5 0 1 2 3 4 5 6
Supply Voltage VDD [V]
28
PD75B316B
SERIAL TRANSFER OPERATIONS 2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS VDD = 4.5 to 6.0 V
MIN. 1600 3800
TYP.
MAX.
UNIT ns ns ns ns ns
SCK cycle time
tKCY1
SCK high-/lowlevel width SI setup time (to SCK ) SI hold time (from SCK ) SO output delay time from SCK
tKL1 tKH1
VDD = 4.5 to 6.0 V
tKCY1/2-50 tKCY1/2-150 250
tSIK1
tKSI1 VDD = 4.5 to 6.0 V
400 250 1000
ns ns ns
tKSO1
RL = 1 k, CL = 100 pF*
2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 SCK high-/lowlevel width SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK2
tKSI2 VDD = 4.5 to 6.0 V
400 300 1000
ns ns ns
tKSO2
RL = 1 k, CL = 100 pF*
*
RL and CL are the SO output line load resistance and load capacitance.
29
PD75P316B
SBI Mode (SCK ... Internal clock output (Master)): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY3 3800 SCK high-/lowlevel width SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tKL3 tKH3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 250 ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns
tSIK3
tKSI3 VDD = 4.5 to 6.0 V
tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns ns
tKSO3
RL = 1 k, CL = 100 pF*
tKSB tSBK tSBL tSBH
SBI Mode (SCK ... External clock input (Slave)): (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
PARAMETER SCK cycle time SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V tKCY4 3200 SCK high-/lowlevel width SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width tKL4 tKH4 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK4
tKSI4 VDD = 4.5 to 6.0 V
tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns ns
tKSO4
RL = 1 k, CL = 100 pF*
tKSB tSBK tSBL tSBH
*
RL and CL are the SBO, 1 output line load resistance and load capacitance.
30
PD75B316B
AC Timing Test Points (Except X1 and XT1 inputs)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timings
1/fX tXL tXH
X1 Input
VDD -0.5 V 0.4 V
1/fXT tXTL tXTH
XT1 Input
VDD -0.5 V 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
31
PD75P316B
Serial Transfer Timing 3-wired serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI tKSO1
Input Data
SO
Output Data
2-wired serial I/O mode:
tKCY2 tKL2 tKH2
SCK tSIK2
tKSI2
SB0,1
tKSO2
32
PD75B316B
Serial Transfer Timing Bus release signal transfer:
tKL3,4 tKCY3,4 tKH3,4
SCK tSIK3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1
tKSO3,4
Command signal transfer:
tKCY3,4 tKH3,4
tKL3,4
SCK tSIK3,4
tKSB
tSBK
tKSI3,4
SB0,1 tKSO3,4
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4 KR0-7
RESET Input Timing
tRSL
RESET
33
PD75P316B
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +85 C)
PARAMETER Data retention supply voltage Data retention supply current*1 Release signal setting time Oscillation stabilization wait time*2 SYMBOL VDDDR IDDDR tSREL Release by RESET tWAIT Release by interrupt request *3 ms VDDDR = 2.0 V 0 217/fx TEST CONDITIONS MIN. 2.0 0.3 TYP. MAX. 6.0 15 UNIT V
A s
ms
* 1. Excluding current flowing in the internal pull-up resistor. 2. The oscillation stabilization time is the time during which the CPU operation is stopped to prevent unstable operation when oscillation is started. 3. Depends on the basic interval timer mode register (BTM) setting ( see table below).
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
WAIT TIME (Figure in ( ) is for fx = 4.19 MHz) 220/fx (Approx. 250 ms) 217/fx (Approx. 31.3 ms) 215/fx (Approx. 7.82 ms) 213/fx (Approx. 1.95 ms)
34
PD75B316B
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
35
PD75P316B
DC PROGRAMMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER Input voltage high SYMBOL VIH1 VIH2 VIL1 VIL2 IL1 VOH TEST CONDITIONS Except X1, X2 X1, X2 Except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA VDD -1.0 MIN. 0.7 VDD VDD -0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 UNIT V V V V
Input voltage low Input leakage current Output voltage high Outputvoltage low VDD supply current VDD supply current
A
V
VOH
IOL = 1.6 mA
0.4
V
IDD IPP MD0 = VIL, MDI = VIH
30 30
mA mA
Note
1. Ensure that VPP does not exeed +13.5 V including overshoot. 2. VDD must be applied before VPP, and cut after VPP.
36
PD75B316B
DC PROGRAMMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER Address setup time*2 (to MD0) MD1 setup time (to MD0) Data setup time (to MD0) Address hold time*2 (from MD0) Data hold time (from MD0) Data output float delay time from MD0 VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) Data output delay time from MD0 MD1 hold time (from MD0) MD1 recovery time (from MD0) Program counter reset time X1 input high-/low-level width X1 input frequency Initial mode setting time MD3 setup time (to MD1) MD3 hold time (from MD1) MD3 setup time (to MD0) Data output delay time from address*2 Data output hold time from address*2 MD3 hold time (from MD0) Data output float delay time from MD3 SYMBOL tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tACC tOH Program memory read Program memory read Program memory read Program memory read Program memory read 2 2 2 2 2 0 2 2 130 *1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR MD0=MD1=VIL tM1H+tM1R 50 s 2 2 10 0.125 4.19 TEST CONDITIONS MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 1 1.0 1.05 21.0 130 TYP. MAX. UNIT
s s s s s
ns
s s
ms ms
s s s s s s
MHz
s s s s s s s s
* 1. Symbol of corresponding PD27C256A 2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin.
37
PD75P316B
Program Memory Write Timing
tVPS VPP VPP VDD VDD + 1 VDD VDD tVDS tXH
X1 tXL P40 - P43 P50 - P53 t1 MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tM0S tOPW Data Input tDS tDH Data Output tDV tDF tDS Data Input tDH tAH tAS Data Input
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD + 1 VDD VDD tXH X1 tXL P40 - P43 P50 - P53 t1 MD0 tDV Data Output tDAD tHAD Data Output tDFR tM3HR
MD1 tPCR MD2 tM3SR MD3
38
PD75P316B
6. PACKAGE INFORMATION
80 PIN PLASTIC QFP ( 14)
A B
60 61
41 40 detail of lead end
D
C
S
80 1
21 20
F
G
H
IM
J
K P
N
L S80GC-65-3B9-3
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q S
MILLIMETERS 17.2 0.4 14.0 0.2 14.0 0.2 17.2 0.4 0.8 0.8 0.30 0.10 0.13 0.65 (T.P.) 1.6 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX.
M
INCHES 0.677 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.677 0.016 0.031 0.031 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.063 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
55
Q
39
PD75P316B
80 PIN PLASTIC TQFP (FINE PITCH) (
A B
12)
60 61
41 40
detail of lead end
C
D
S Q
80
21 1 20
F
G
H
I
M
J
K
P
N L
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS A B C D F G H I J K L M N P Q R S 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009
M
0.145 +0.055 0.0060.002 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4
40
R
PD75P316B
80 PIN CERAMIC WQFN
A B K
Q
T
U1
C
D
W
80 H IM J 1 R
U
Z X80KW-65A-1 NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K Q R S T U U1 W Z MILLIMETERS 14.0 0.2 13.6 13.6 14.0 0.2 1.84 3.6 MAX. 0.45 0.10 0.06 0.65 (T.P.) 1.0 0.15 C 0.3 0.825 0.825 R 2.0 9.0 2.1 0.75 0.15 0.10 INCHES 0.551 0.008 0.535 0.535 0.551 0.008 0.072 0.142 MAX. 0.018+0.004 -0.005 0.003 0.024 (T.P.) 0.039+0.007 -0.006 C 0.012 0.032 0.032 R 0.079 0.354 0.083 0.030+0.006 -0.007 0.004
F
G
S
41
PD75P316B
7.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions for the surface mounting type, refer to the information
document "Surface Mount Technology Manual (IEI 1207)". For soldering methods and conditions other than those recommended below, contact our salesman. Table 7-1 Recommended Soldering Conditions
PD75P316BGC-3B9: 80-Pin Plastic QFP (s 14 mm) s
Soldering Method Recommended Soldering Conditions Package peak temperature: 230C; Duration: 30 sec. max. (at 210C or above); Number of times: once; Pin part temperature: 300C max.; Duration: 3 sec. max. (per device side) Recommended Condition Symbol
Infrared reflow
IR35-00-1
Pin part heating
PD75P316BGK-9: 80-Pin Plastic QFP (s 12 mm) s
Soldering Method Recommended Soldering Conditions Recommended Condition Symbol
Package peak temperature: 235C; Duration: 30 sec. max. (at 210C or above); Infrared reflow Number of times: once; Timelimit: 7 days*(thereafter 10 hours prebaking required at 125C) Pin part heating Pin part temperature: 300C max.; Duration: 3 sec. max. (per device side)
IR35-00-1
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65% RH. Use of more than one soldering method should be avoided (except in the case of pin part heating).
Note
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PD75P316B
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD75P316B.
IE-75000-R*1 IE-75001-R IE-7500-R-EM*2 EP-75308BGC-R Hardware EV-9200GC-80 EP-75308BGK-R EV-9500GK-80 PG-1500 PA-75P316BGC PA-75P316BGK Software IE control program PG-1500 controller RA75X relocatable assembler 75X series in-circuit emulator Emulation board for IE-75000-R and IE-75001-R Emulation probe for PD75P316BGC. Provided with EV-9200GC-80, 80-pin conversion socket.
PD75P316BGK emulation probe.
Provided with EV-9200GK-80, 80-pin conversion socket. PROM programmer
PD75P316BGC programmer adapter. Connected with PG-1500. PD75P316BGK programmer adapter. Connected with PG-1500.
Host Machine PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3) IBM PC/ATTM (PC DOSTM Ver.3.1)
*
1. Maintenance product 2. Not incorporated in the IE-75001-R. 3. The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software.
5
43
PD75P316B
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name User's Manual Instruction Application Table Application Note 75X Series Selection Guide Document Number IEM-5016 IEM-994 IEM-5035 IEM-5041 IF-151
Development Tools Documents
Document Name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75308BGC-R User's Manual EP-75308BGK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language Document Number EEU-846 EEU-673 EEU-825 EEU-838 EEU-651 EEU-731 EEU-730 EEU-704
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality Grande on NEC Semiconductor Device NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge(ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufacturers Volume Document Number IEI-635 IEI-1207 IEI-1209 IEM-5068 MEM-539 MEI-603 MEI-604
*
The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc.
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PD75P316B
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PD75P316B
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6

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